The present disclosure generally relates to semiconductor devices, and particularly to field effect transistors including an embedded source/drain region that contains a graded-doping semiconductor material portion, and methods of manufacturing the same.
A “late epitaxy process,” in which formation of deep source and drain regions is performed after formation of source and drain extension regions, provides advantage over an “early epitaxy process” by enabling as-grown doping of the deep source and drain regions. The early epitaxy process refers to an epitaxy process that is followed by deep source/drain implantation and an activation anneal at a relatively high temperature. The late epitaxy process eliminates the need for deep source/drain implantation, which could relax the epitaxial stress provided by epitaxially grown deep source and drain regions. Late epitaxy can thus allow a higher level of stress to be applied to the channel region of a field effect transistor. The late epitaxy process can also provide various additional advantages.
To provide a low on-resistance for a field effect transistor (FET), hence a high performance FET, a high level dopant concentration and/or a high level of dopant activation are needed in the source and drain regions. However, the increase in the dopant concentration can cause short channel effects through degraded junction profile. Furthermore, a higher level of dopant activation requires an anneal at a higher temperature, which also degrades the junction profile. Thus, the dopants in the source and drain regions need to be activated with minimum degradation in the junction profile in order to minimize short channel effects degrade.
To improve carrier mobility and hence improve FET performance, a high stress level in the FET conduction channel is needed. While the increase in the stress level is possible by increasing the volume of epitaxial stressor materials in embedded source and drain regions, incorporation of more embedded stressor materials requires reducing proximity between the embedded source and drain regions. The close proximity between source and drain causes degraded short channel effects.
In view of the difficulties in enhancing performance of field effect transistors through embedded source and drain stressor materials, a method to minimize the short channel effect while maximizing the stress effects of embedded source and drain region is desired.